Courses

IDESA will organise several 4- or 5-day courses on advanced IC implementation flow, targeting Professors, Post-Docs and PhD-students. These course will tour all over Europe, starting May 2008. All courses will include lectures and also several hands-on sessions.

IDESA course fees are low, only 50 EUR per day, covering the cost for hosting the course and for handouts. PhD students can apply for a 1000 EUR grant covering course fee, travel and subsistence: http://www.eurodots.org/Students.asp. The courses can give you ECTS, being approved by many doctoral schools in Europe. Check with your PhD advisor.

Advanced analog implementation flow

The 5-day analog implementation flow course will start with a short overview of the 90nm IC process flow, it will cover modelling issues, hand calculation versus simulation accuracy, transistor level and behavioral level design, analog cell trimming using digital functions, mixed mode simulation, mismatch and yield modelling and analysis, and analog modelling and circuit optimisation.

Leaflet   Calendar and Registration

"" I found the Analog and the RF implementation courses I attended very useful and of direct relevance to my teaching and research. I found the technical level to be correct with a good balance of reinforcement of current understanding and introduction of new concepts. In many cases, for example for seminar-style presentation, the slides may be used directly without editing. The provision of a soft version of the slides is really useful. The common use of MSOffice tools in the slide construction makes slide selection and catenation easy. ""
(Paul Warr, Bristol University)

Advanced RF implementation flow

The 5-day RF implementation flow course will start with a short overview of the RF 90nm IC process flow, it will cover modelling issues, microwave passive component design and simulation, testing and microwave measurements, mismatch modelling and simulation, mixed-modes SoC design and simulation, analog and RF cell trimming using digital functions, 90 nm design verification, circuit packaging and ESD-protection

Leaflet   Calendar and Registration

"" I really appreciated the IDESA RF implementation course I attended. Overall the course was of high quality both with respect to the lecturers and the content. The didactic material provided seems very useful for reuse at our department and we are planning to develop an intensive course for our students based on this material. "" (Dag Wisland – University of Oslo)

Advanced digital physical implementation flow

The 5-day digital physical implementation flow will start by introducing the challenges for 90 nm SoC design and the design environment and too chain. The course will proceed with digital synthesis, leakage-aware design, design planning and floorplanning, library analysis and management. It will focus upon low power design flow covering techniques to minimise dynamic and static power consumption, multiple clock tree synthesis, test and multimode and multicorner optimisation. IR-drop analysis, dynamic power analysis sign-off and design finishing and layout verification will be covered. Extensive hands-on labs are part of the course.

Leaflet   Calendar and Registration

"" I have attended the course on: “Advanced Digital Physical Implementation flow, Aristotle University of Thessaloniki 16-20 February 2009” It has more than fulfilled my expectations: I have found it:
complete in the overview of the digital design flow for newer technologies; successful in balancing the theoretical and the practical knowledge passed on to the attendees; solid and effective in the lab session for: experience and dedication of the trainers, the choice of tools, the lab examples proposed.
In the end the experience and all the material provided was extremely useful to me as a designer and teacher."" (Angelo Cotta Ramusino – INFN – Ferrara)

Design for manufacturability flow

The 4-day DFM course will introduce the advanced IC manufacturing flow, and will focus upon defectivity, post-layout manufacturability issues such as OPC (optical proximity correction) and will include litho simulations and process window issues. After these process oriented topics, the course will address design and layout for litho manufacturability, with proper attention for the back-end dual damascene copper interconnect issues. There will be hands-on sessions on DFM solutions and Yield analysis, including Design-for-Test and Yield management.

Leaflet   Calendar and Registration

"" I attended the course on Design for Manufacturability and found it to be very interesting and instructive. It was a revelation that the lecturers, all experts in the field, had a clear and fascinating style of presenting the course, profoundly explaining and stressing the important basics of the subject and going into detail when necessary. In the practical sessions, we acquired hands-on experience with the latest tools, with an expert sitting next to you for help. The course material was nicely presented and I regularly retake the slides when I need some information or to explain things to my colleagues."" (Roel Maes, KU Leuven)