Please refer to www.imec-academy.be to get access to these recordings. Search for IDESA, or for the title of the lecture, name of the lecturer,
Please refer to www.imec-academy.be to get access to these recordings. Search for IDESA, or for the title of the lecture, name of the lecturer,
|1||Low Power Digital Design in Sub-90nm CMOS Technologies by Wim De Haene (KULeuven)
Low Power Digital Design in Sub-90nm CMOS Technologies
Wim De Haene (KULeuven)
In this course is shown how low power design is still possible when scaling goes beyond 90 nm.
First a short review of classic power reduction techniques at technology, circuit and architectural level is given. Then it explaines why technology scaling is no longer living up to its classical promises when it comes to power and energy reduction. It is shown that both leakage and technological variability are hampering the striving for energy reduction.
For leakage the different reduction techniques are discussed. Design examples are shown. For variability the problem is even more stringent. Energy increase due to variability is caused by the fact that variability forces the designer to increase the design margin. This is needed to ensure yield even in variable conditions. Increased margins come with over-design and thus with energy increase. This problem is explained in more detail and solution directions are given. However, dealing with variability remains a research subject…
|2||Component matching: best practices and fundamental limits by Marcel Pelgrom and Maarten Vertregt (NXP Research) Component matching: best practices and fundamental limits
Marcel Pelgrom and Maarten Vertregt (NXP Research)
Circuit operation greatly depends on the ability to control and reproduce component parameters, such as resistances, capacitances, transistor currents. Variation in processing was in the past countered by defining process corners: boundaries in parameter variation that accounted for process tolerances. With the improved control over processing, this batch-to-batch variation is largely under control.
However, now a new class of phenomena has appeared: statistical variations. In conventional ICs, analog circuits with a differential operation (e.g. analog-to-digital converters) were already affected by this random parameter spread. At the sub 90-nm nodes also digital circuits are affected. The variation between otherwise identical components is generally described by “mis-match” parameters. The “offset” part of mismatch is due to predictable effects in lithography, current routing etc and can be reduced by proper design. The random part is due to stochastic processes. Understanding and mitigating these effects requires more and more statistical means.
The talk focuses on mechanisms, which originate from physical, electrical, technological effects causing these intra-die variations.
|3||Automotive Interferences: EMC and Transients by Herman Casier Automotive Interferences: EMC and Transients by Herman Casier
Automotive electronics are very demanding due to their very high safety and reliability requirements and the harsh environment in which they operate. The main design challenge sposed by this harsh environment translate in a high voltage supply with high power transients, a high ambient temperature and high electromagnetic and electrostatic interferences. The EMC and ESD interferences and the power supply transients are the topic of this lecture.
EMC in particular is a difficult topic to cope with during design. EMC in general is first discussed: basic characteristics, how it can be made compatible with classical IC design tools, standards and measurement methods at IC and system level.
Electro-Magnetic Emission at chip level (EME) is then discussed: what happens, how to cope with at chip, package and PCB level, high level modeling of the IC for system simulations. Low EME design techniques such as selection of logic family, clocking strategy,on-chip decoupling and internal regulation are then described.
Electro-Magnetic Immunity (EMI) is the next topic. Its main disturbing effects are rectification and pumping, parasitic activation and power dissipation issues. High EMI design techniques are described in various circuits such as current and voltage references, opamps and comparators.
The last topic describes the standardised conducted and coupled power supply transients. Failures, generated by these transients are generally due to substrate currents, which require different methods to cope with.
|4||Reliability of future advanced CMOS circuits and technologies by Guido Groeseneken (IMEC) Reliability of future advanced CMOS circuits and technologies
Guido Groeseneken (IMEC)
In this lecture the basic reliability problems of advanced CMOS devices is discussed. First Guido gives some basic concepts related to the field of reliability (definitions, statistical distributions, accelerated testing, acceleration models etc.). Then he discusses three major degradation problems, related to MOSFET reliability: Time-Dependent Dielectric Breakdown (TDDB, Negative-Bias Temperature instability (NBTI) and Electrostatic Discharge (ESD). For each of these problems he discusses the origin, the physical and acceleration models and the implications on circuits. He also discusses the problem of ESD protection for RF-applications as well as possible solutions that have been proposed. Finally he shows that the 'classical' approach of reliability assessment will no longer be feasible in future technologies, and he demonstrates the need for more interaction between designers and process and reliability engineers in a so-called Reliability-Aware design approach to guarantee reliable operation of future IC's.
|5||Two important transistor innovations: strained silicon and FinFETs by Geert Eneman - Nadine Collaert (IMEC) Two important transistor innovations: strained silicon and FinFETs
Geert Eneman - Nadine Collaert
In this lecture, two important transistor innovations will be discussed: strained silicon and FinFETs. It will be shown that, while these techniques allow further scaling of CMOS dimensions, they also put an extra complication to digital and analog design. Mobility enhancement through mechanical strain is one of the key enablers to scale silicon CMOS beyond the 90nm node. This lecture will give an overview of the influence of strain on mobility and MOS device characteristics. After this, various practical techniques to apply strain to a MOSFET will be discussed. It will also be shown that the effectiveness of several strain techniques depends on transistor dimensions, as well as on layout. This problem will be explained, and guidelines will be given to minimize this effect. FinFETs and in general multi-gate devices have been the subject of many publications over the last decade. The multi-gate MOSFET is considered as one of the most promising device architectures for scaling CMOS beyond the 45nm technology node. The benefits of these devices are reduced short channel effects, leakage currents and VT dopant fluctuations due to the undoped channels. Starting from the theory, the advantages but also the challenges of this device architecture will be discussed. Some layout specific issues will be addressed and finally, an overview of the performance of FinFET circuits will be presented.
|6||Risk free, 65 nm and beyond, digital low power design by François Thomas (Cadence) Risk free, 65 nm and beyond, digital low power design
François Thomas (Cadence)
Power considerations in portable and wireless consumer devices have become a key part of many product specifications. Even for wired devices and other industry segments in which battery power has not traditionally been an issue, considerations of packaging, reliability, and cooling costs bring power firmly to the forefront at smaller geometries. In particular, as designs migrate to 65nm and beyond process nodes, power management becomes a serious concern across the entire design and manufacturing chain.
To achieve the required power targets, design teams are increasingly adopting advanced power management techniques such as multi-supply voltage (MSV) and power shut-off (PSO). Such techniques, however, increase design complexity and introduce risk.
This lecture will detail power management techniques, static and dynamic, required at 65nm and beyond:
|7||Variability Aware Modeling and Yield Aspects by Bart Dierickx (IMEC) Variability Aware Modeling and Yield Aspects
Bart Dierickx (IMEC)
We describe the basic sources of variability, this includes MOSFET variability and interconnects (R, C) variability. We describe the IMEC approach to model variability throughout the whole design flow, include a description of the different steps necessary to apply such flow on a real life design. Aspects as local vs global variability, correlations, andstatistical methods are introduced. The methodology builds on top of existing signoff and simulations flows, and "adds" or "enables" variability throughout the different abstract levels of the digitalelectronic design. In a second more speculative part we address some aspects of variability as a function of time, i.e. "degradation" or "reliability" mechanisms. How could these be represented on a variability modeling flow? What is the expected outcome?
|8||Variability and Litho-aware digital implementation by François Thomas (Cadence)Variability and Litho-aware digital implementation
François Thomas (Cadence)
To successfully get nanometer-scale designs to market, semiconductor companies must address a growing array of challenges. Designers must contend with the physical effects that become much more troublesome at these smaller geometries. Lithography and CMP manufacturing effects can have significant impact on both functional and parametric yield. Process variations across the die, wafer, and batch affect yield, performance, and reliability.
This lecture will detail those new difficulties:
|9||Leakage physics and modeling by Wieslaw Kuzmicz (Warsaw University of Technology)
Leakage physics and modeling
Wieslaw Kuzmicz (Warsaw University of Technology)
In deep submicron CMOS static gates static power consumption is no longer negligible due to large static currents that flow in the devices in their " off " state. This lecture discusses the origins of these currents: subthreshold current, gate tunneling current, junction tunneling currents and other static currents. The goal is to explain how these currents depend on the device design (process and layout) and its operating conditions (such as VDD and body bias). It is also shown how these currents are represented in the MOS device compact models.
Effects of process variability on leakage are also discussed. Highly nonlinear dependences of some leakage currents on process and device design result in non-Gaussian statistical distributions. Asa result, high process variability inherent in deep submicron processes not only results in high variability of the leakage, but also leads to increase of the mean values of the leakage currents and increase of the total static current consumption.
Exercises will include examples of hand (or Excel-based) calculations of various leakage components as functions of device design and its operating conditions.
|10||Techniques to control leakage power at technology and device level : application to a fully power aware SoC design by Edith Beigné (CEA)
Techniques to control leakage power at technology and device level : application to a fully power aware SoC design
Edith Beigné (CEA)
As technology is scaled, circuits have to be more and more power effective either in terms of dynamic power or in terms of leakage. This presentation will deal with the technological possibilities to reduce leakage. That means presenting different devices architectures, taking into account variability and processes maturity. As technology cannot do all the job, the second part of the talk is focusing on design techniques to reduce leakage power and dynamic power considering SoC implementation. We will first focus on state of the art, explaining existing techniques at design level. Those new design methodologies have been explored in order to lower the total power consumption of a complex SoC called ALPIN "Asynchronous Low Power Innovative NoC". This circuit has been designed in order to qualify different design techniques aiming at reducing both dynamic and static power consumption in a 65 nm CMOS technology. Different techniques as voltage scaling, Vdd hopping and power switches insertion have been implemented on a complete GALS system. Physical implementation issue and use of standard CAD flows will also be addressed.
|11||Compact models for DSM by Christian Enz (EPFL)
Compact models for DSM
Christian Enz (EPFL)
The combination of decreasing MOSFET dimensions and increasing use of MOSFETs for analog and RF application has created the need for advanced compact models for MOSFET circuit design. The first generation of MOSFET models rely on approximate solutions that start to show some fundamental limitations when used for designing circuits in advanced nano-scale technologies. This lecture addresses the most important issues that directly impact the performance and design of circuits and that have to be accounted for in future compact models. Effects such as short-channel effects, gate tunneling current, device matching, thermal noise, flicker noise are discussed. It also provides an overview of the basic physics that must be modeled to build a compact model for the MOSFET and describes the approaches taken by the developers of several advanced models, including PSP and EKV. Finally, an overview of new device structures such as double-gate and multi-gate devices is also given.
|12||Statistical Static Timing Analysis and Optimization - François Thomas (Cadence)
Statistical Static Timing Analysis and Optimization
François Thomas (Cadence)
Traditional STA accounts for process variations by introducing more aggressive gross guardband and using multiple analysis corners to model different process and environmental variation combinations. This corner-based approachcan be overly pessimistic since it reports timing scenarios that have an extremely small likelihood of occurring. Also, the exponential growth in the number of corner combinations with the increasingnumber of parameters makes analysis on every corner impractical.
Beyond 65nm, pessimism introduced by the multicorner approach is just no more affordable, Statistical STA accounts for the variability of process parameters in a single run. It uses advanced statistical models to identify cells and nets on both clock and data paths that are sensitive to variations, and also determines the probability of timing failure over the full range of process variation. This reduces pessimism and allows for reduced Guardbanding, resulting in decreased area and power consumption while improving chip performance. It lets designers explore potential tradeoffs between parametric yield and clock speed.
This lecture will detail the principles of SSTA, the requirements in term of modelisation as well as how it should be incorporate in a variability aware design flow, both in term of analysis and optimization.
|13||CMOS front-end design at millimetre wave frequencies - Alexandre Siligaris (CEA LETI)
CMOS front-end design at millimetre wave frequencies
Alexandre Siligaris (CEA LETI)
CMOS technologies are very attractive for microwave applications. Indeed, the cut-off frequencies (fmax and ft) of CMOS transistors exceed 200GHz in current ultimate technology nodes (65nm and 45nm). Thus, it is possible to fabricate low cost millimetre wave circuits for applications such as wireless communication systems with multi Gigabit/sec data rate (Wireless HD, WPAN IEEE 15.3c). In order to design such circuits, a good knowledge is needed of both CMOS technologies and microwave design techniques. In this seminary, we will present the CMOS technologies and their high frequency performance and limitations. Emphasis will be put on the modelling techniques of active and passive elements which are needed for accurate design. In addition, microwave measurement issues will also be addressed. Finally, we will show design examples of building blocks of a millimetre-wave front-end (Low Noise Amplifier, Mixer, Voltage Controlled Oscillator, Power Amplifier).
|14||Analog design in scaled technologies - Andrea Baschirotto (University of Lecce)
Analog design in scaled technologies
Andrea Baschirotto (University of Lecce)
The running CMOS technology scaling (down to 65nm and 45nm) has a big impact in the design of analog circuits. Since scaled technologies offer big advantages to digital parts (reduce space, lower power consumption, etc...), complex mixed-signal systems are typically developed in the smallest minimum-gate-length technology. However these advantages for the digital part in a scaled technology correspond to a big penalty in the analog design. Typical problems are due to the lower output impedance, to the lower available output swing and to the lower distance from VDD to VTH (VDD scales faster than VTH). Analog designers have then to develop new solutions for achieving in scaled technologies the same performance previously achieved in "older" technologies. In the lecture these problems will be addressed for the cases of basic building blocks like current mirrors, bandgaps, gain stages. We will discuss if the solution adopted in 90nm technologies could be ported to 65nm/45nm and (if not) how they can be realized with new topologies. Then the discussion will move to their effects on complex systems (analog filter and data-converters) showing the possible solution in 65nm/45nm, discussing the unavoidable design trade-offs.
|15||Design of ADC in advanced technologies - Andrea Baschirotto (University of Lecce)
Design of ADC in advanced technologies
Andrea Baschirotto (University of Lecce)
A key block of mixed-mode signal processing is the ADC, which often connects the analog world with the internal DSP. ADC's can be realized with several architectural topologies and several circuit solutions. The selection among them is done with the trade-off between the application target specification and the available technology features. In advanced IC technologies scaled CMOS devices features lower supply voltage operation, higher speed-of-response and lower dc-gain. These performance modifications are changing the ADC design scenario that is now considering in particular the architectural and circuit solutions taking advantage of these devices performance. In this tutorial the critical point in the design of the basic building blocks common to any ADC topologies are depicted. After this, the case of SAR ADC which appears the topology, which takes the full advantages of the scaled technologies, is addressed in details.
|16||Design of analog filters in advanced technologies - Andrea Baschirotto (University of Lecce)
Design of analog filters in advanced technologies
Andrea Baschirotto (University of Lecce)
Analog filters are basic building blocks in the analog signal processing. A large number of possible implementation techniques are proposed in literature. All of them have now to be considered in the realization of analog filter to be realized in scaled technologies where the CMOS devices are offering larger speed-of-response but lower dc-gain. In this tutorial several analog filter implementation solutions are presented (Active-RC, Gm-C, source-follower-based, etc…), illustrating their main characteristics, achievable performance and main performance limitations. This tutorial will allow the designer to analyze and to select the most appropriate filter topology for his target application.
|17||Low power CMOS 65 and 45 nm industrial technologies - Thomas Skotnicki (STMicroelectronics)
Low power CMOS 65 and 45 nm industrial technologies
Thomas Skotnicki (STMicroelectronics)
The 65nm and 45nm CMOS technologies have probably been the most interesting ones from the time of such big innovations as poly-Silicon gate or STI isolation. The intensity of parasitic effects due to aggressive scaling came to summit, and obliged the semiconductor industry to apply radical remedies at these nodes. In this course we will explain the parasitic effects and the limitations they set for CMOS technologies (performance, leakage) and circuits (power consumption, speed, variability, yield). We willexplainthe physics of SCE, DIBL, subthreshold slope, leakage, gate tunneling, mobility degradation, variability, etc. in different transistor structures.
We will also present multiple gate oxide approach, multiple threshold voltages,back-biasing, and other approaches permitting better performance and power efficiency. Circuit level implications in terms of leakage, inverter delay, power consumption and SRAM stabilitywill be compared and explained for different transistor structures and technological approaches. Finally, a longer term perspective will be given regarding CMOS scaling towards nano-devices and terabit circuits.
|18||ESD and Latchup - Fabrice Blanc (ARM)
ESD and Latchup
Fabrice Blanc (ARM)
ESD effects in integrated circuits have become a major concern as today's technologies shrink to deep-submicron dimensions. The CMOS technology roadmap predict aggressive scaling down of device size, transistor threshold voltage, oxide and metal thicknesses to meet the growing demands for higher levels of integration and performance. Such progress for CMOS circuits in the nanometer regime will increase leakage current exponentially, secondly will cause more variability in device parametric and finally will limit electromigration across the different metal layers. In addition of that, the thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. These technology evolutions are limiting the ESD design window. The challenges associated with the design and implementation of Electrostatic Discharge protection circuits are becoming increasingly complex as technology is scaled into nano-metric regime. Traditional approaches of ESD design may not be adequate as the ESD damages occur at successively lower voltages in nano-metric dimensions. There areseveral challenges that must be met in order to design robust ESD circuits today. The ESD protection design for current and future sub-45nm CMOS circuits is a challenge for high I/O count, multiple power domains.
|19||DFT to meet Nanometer Test Challenges - Philippe Rossant (Synopsys)
DFT to meet Nanometer Test Challenges
Philippe Rossant (Synopsys)
This lecture presents how Nanometer Technologies are impacting Design For Test (DFT) and Automatic Test pattern Generation (ATPG). Goal is to achieve high quality results in record time with more complex/hard to find defects, and also to manage the cost of quality in an environment of increasing design complexity. We focus on rapid and predictable concurrent design flow to achieve DFT Closure (namely power aware DFT and ATPG, timing aware DFT and ATPG, physically aware DFT, and also manufacturing aware diagnostics to improve yield). Since single stuck at fault model does not allow to keep good silicon correlation, new fault models are introduced such as static/dynamic bridging fault, at-speed testing (with transition fault, path delay fault, and small delay defects) while on chip clocking support has to be properly handled by both DFT and ATPG. In such context of increasing complexity, Adaptative Scan Compression (both in DFT and ATPG domains) is then introduced, because such DFT is becoming more and more mandatory today, to be compliant with all of these goals and requirements.
|20||Ultra-low Voltage Analog Circuit Design - Christian Enz (CSEM SA, Neuchatel - EPFL, Lausanne)
Ultra-low Voltage Analog Circuit Design
Christian Enz (CSEM SA, Neuchatel - EPFL, Lausanne)
The supply voltage of CMOS chips has constantly been scaled down in the last years to reach now the sub-1V region. This supply voltage reduction is mainly driven on one hand by the technology constraints to maintain a reasonable electric field within the MOS device to avoid high-field effects and on the other handby the needs of digital circuits to reduce the dynamic power consumption. Analog circuits unfortunately don't take any advantage of this voltage down-scaling since almost all their performances are degraded and some basic circuits would even stop operating correctly. We will discuss the main challenges faced when designing analog circuits for ultra-low voltage (ULV) operation. We will first present the fundamental limits set by ULV, together with the technology limitations (such as matching) for analog circuits. We will then have a closer look at the MOS transistor operation with a particularfocus on weak inversion, the Gm/ID characteristic and the inversion coefficient design approach. We then will review several basic building blocks capable of operating at ULV, including both continuous-time and sampled-data circuits. Finally we will investigate the potential of designing RF circuits in ULV taking advantage of ultra-deep submicron processes and give some design examples.
|21||Advanced circuit design in ermerging 2D & 3D SOI technologies - Thierry Poiroux (CEA LETI)
Advanced circuit design in ermerging 2D & 3D SOI technologies
Thierry Poiroux (CEA LETI)
This presentation will give an overview of specific SOI developments in the field of technology and modelling. Regarding the modelling, we will detail the way SOI effects such as floating body effectsrelated to partially depeleted substrates or interfaces coupling, undoped channels in fully depleted substrates are taken into account in accurate compact models. We will also address the technological issues linked to SOI such as access resistance optimization (doping and epitaxy for raised source and drain), threshold voltage adjustment (use of metal gate) and transport.
|22||SOI and multiple gate transistors - Thierry Poiroux (CEA LETI)
SOI and multiple gate transistors
Thierry Poiroux (CEA LETI)
We will see in detail the way SOI effects such as floating body effectsrelated to partially depeleted substrates or interfaces coupling, undoped channels in fully depleted substrates are taken into account in accurate compact models. We will also address the technological issues linked to SOI such as access resistance optimization (doping and epitaxy for raised source and drain), threshold voltage adjustment (use of metal gate) and transport.
|23||Thermal issues in nanoscale VLSI devices and circuits - Nicolo Rinaldi (University of Naples)
Thermal issues in nanoscale VLSI devices and circuits
Nicolo Rinaldi (University of Naples)
Power dissipation trends in VLSI circuits and emergence of thermal issues, Power dissipation in CMOS and BICMOS circuits, CMOS operation , CMOS static and dynamic power dissipation , Bipolar transistor operation , Power dissipation in bipolar transistors, Reliability issues , Heat transfer basics and thermal management , Heat transfer mechanisms , Thermal resistance , Thermal impedance and thermal capacitance ,...
|24||Statistical Memory Analysis for robust SRAM design - Paul Zuber, Petr Dobrovolny (imec)
Statistical Memory Analysis for robust SRAM design
Paul Zuber, Petr Dobrovolny (imec)
This seminar presents Memory Variability Aware Modeling (or MemoryVAM), a tool and approach to perform SRAM wide statistical analysis in presence of process variability. The first part of the seminar will motivate why this approach successfully captures non-trivial statistical interactions between the cells and the periphery, which remain uncovered when only using statistical electrical simulations of the critical path or applying a digital corner approach. The tool provides the designer with valuable information on what performance metrics and yield to expect, if manufactured. The second part of the seminar will be devoted to present the set of techniques supporting the approach. Results on production-ready 45 and 32 nm SRAM designs show that MemoryVAM is significantly more accurate than the alternatives based on global corners or statistical memory access path analysis, which can lead to unexpected yield loss. Since this feedback takes place in the design phase, a significant reduction in development time and cost can be achieved.
|25||Metric Driven Verification - Hans Zander (Cadence)
Metric Driven Verification
Hans Zander (Cadence)
The Metric Driven Verification Methodology reduces risk in the verification of full chips and SoCs by providing a system of best knownprinciples, practices, and procedures that increase project productivity and predictability and ensure overall system-level quality. A guiding principle of the Plan-to-Closure Methodology is to "begin with the end in mind." Accordingly, the methodology spans the full verification process from creating automated, executable plans to achieving system-level closure. The Plan-to-Closure Methodology is a map that steers verification based on optimized methods that have been tested on real projects. It meets the broad spectrum of verification needs, from designers verifying blocks, to design teams, to enterprise multi-specialist teams who rely on the most advanced verification techniques.
|26||Assertion-based verification - Kawe Fatouhi (Cadence)
Kawe Fatouhi (Cadence)
The exponential growth in complexity of VLSI has been going on for several decades now, and shows no signs of letting up. This growth has strained our capacity to design, and in particular to verify, VLSI devices. The VLSI design industry is constantly innovating-introducing new methodologies and new technologies to deal with this complexity growth. One promising technology that has been developed in recent years is Assertion-Based Verification (ABV) using formal and simulation-based analysis tools. The purpose of this lecture is to provide anoverview of ABV and Formal Analysis and to provide an overview of the Cadence Incisive Formal Verifier tool and the required verification methodology to apply these leading edge verification technologies.
|27||A guided tour of the Interconnect road map from 90 nm down to 32 nm designs in the analog and digital domains - Roberto Suaya
A guided tour of the Interconnect road map from 90 nm down to 32 nm designs in the analog and digital domains
We give an extended presentation on Interconnects from the design and modeling perspective. The first part is dedicated to the implications of technology (node) on the interconnect capabilities. The increased role of process variations, the appearance of new physical boundaries in interconnect while moving up in the Moore law such as scattering phenomena, proximity, skin effects and substrate effects. Some suitable tools to extract the R, C, L parameters are introduced. The second part explores the timing and noise computations associated with the basic physical components: Resistance, Capacitance, Inductance and their cross couplings. Discrete circuit views and continuous EM views are presented. The frequency dependence of the physical parameters R, L and C is explained. On the third and last part we review the system level modeling of interconnect (including passive devices) as needed for the creation of digital and analog Integrated Circuits. The demands on accuracy and computability lead us into the subfields of model order reduction and passivity preservation of linear systems. Examples
|28||Electrostatic discharge protection for DSM RF circuits - Dimitri Linten
Electrostatic discharge protection for DSM RF circuits
This course gives an overview of available techniques and design principles that provide ESD protection for circuits implemented in 90nm CMOS and beyond.
|29||Fundamentals of digitally-assisted RF - Robert Staszewski
Fundamentals of digitally-assisted RF
RF circuits, when implemented in nanoscale CMOS and, especially, when integrated in an SoC, suffer from numerous issues, such as poor linearity, device mismatch, low Vdd headroom, high leakage, high flicker and substrate noise, etc. At the same time, the digital gates and memory are 'free' and powerful, so the logical step is to use digital means to mitigate the RF circuit imperfections so that their adjusted performance can match or exceed that of traditional RF circuits. This tutorial first examines opportunities of digital assistance of RF and then presents case studies of calibration due to process spread, compensation due to environmental changes, performance tuning, automatic reconfigurability, and built-in self-test.
|30||SOC in 65 nm and below. Concepts, design, implementation and application - Fabien Clermidy, CEA-LETI
SOC in 65 nm and below. Concepts, design, implementation and application
Fabien Clermidy, CEA-LETI
To solve the limitations of bus-based SoC designs in terms of bandwidth as well as complexity management, we need new interconnect structures, called Network-on-Chip. NoC concept proposes scalable communications with high bandwidth. It aims at simplifying the design thanks to a unified approach of communications, allowing technology-dispersion tolerant and power efficient structures. However, NoC based design needs to overcome difficulties such as application mapping on a massively parallel structure. The lecture introduces the NoC concepts and reviews the state-of-the-art of this research field. It also shows an applicative NoC implementation to underline the concepts. The attendees will learn the benefits to use a NoC in their design, the way to do it, and will have some elements to understand the application mapping issue.
|31||Heterogeneous Design - Nicolas Delorme, Asygn
Nicolas Delorme, Asygn
The design of heterogeneous microsystems (e.g. MEMS & readout electronics) has become an increasingly complex task mainly because of the variety of disciplines involved and the level of performance needed on the applications side. Recent industrial success stories have proven that cost- and performance-optimized microsystems often require simultaneous co-design of all the components making up the global system. This seminar covers the methodologies, tools and techniques needed for the design of heterogeneous microsystems. Several practical design cases in the fields of MEMS sensing, actuating and energy harvesting are presented and the results compared to the state of the art in terms of readout resolution, bandwidth and power consumption.
|32||Millimeter-wave Design in Silicon Technologies - Didier Belot (STMicroelectronics)
Millimeter-wave Design in Silicon Technologies
Didier Belot (STMicroelectronics)
This presentation will cover the different aspects of the design, from the applications to the implementations in silicon technologies. After an introduction giving us the context of the market interest for the mmW silicon and a presentation of the emerging applications and standards over the world, we will detail the mmW technology features of advanced CMOS and BiCMOS in order to evaluate their potentialities for mmW applications. This technology evaluation will begin by the transistor features, and will continue by an analysis of the Back End Of Line (BEOL) and the substrate contributions in the energy transmission. A comparison of the different design techniques from the building blocks to the transceiver in such technologies will be exposing, and we will try to define some guidelines to help the designers in their choices. Finally we will have a look at the last but not the least performances impactors; I mean the package and the antennas. We will study different state of the art work presented recently and see how the package is completely linked to the circuit design strategy. The conclusions of this tutorial will summarize the advantages and drawbacks of using silicon technologies.
|33||CMOS Radio Wave Design for MM-Wave applications - Piet Wambacq
CMOS Radio Wave Design for MM-Wave applications
Thanks to downscaling, CMOS has become fast enough to handle signals at mm-wave frequencies. Some applications with mass market potential have been identified and are being standardized for operation in a 7GHz frequency band around 60GHz. Among these applications, which exploit the large available bandwidth, we find wireless streaming of uncompressed high-definition video, fast wireless download of Gbytes of data, wireless docking stations, ...
The differences between radios for mm-wave wireless applications and radios for wireless applications below 10 GHz mainly arise from the high RF frequency. For example, at 60GHz the propagation in free space exhibits 100 times more path loss than at 6GHz, due to the ten times shorter wavelength. To relax the link budget, beamforming with phased antenna arrays is often used. The size of antenna arrays is acceptable as antenna size scales down proportional to the wavelength. The implementation of beamforming in CMOS radios is an emerging research topic. Another consequence of the high operating frequency is the need to model interconnects of more than a few tens of micrometers need to be modeled as transmission lines. This complicates the IC design flow.
In this lecture, we will treat different aspects of mm-wave CMOS radios. First, a link budget will be discussed based on specifications from the IEEE standard on 60 GHz wireless communication. Next, beamforming architectures will be analyzed. Finally, circuits used in these architectures will be discussed as well as some specific mm-wave design issues.
|34||Nonlinear distortion analysis in circuits and systems - Prof. dr. ir. Gerd Vandersteen – Dr. ir. Ludwig De Locht (Vrije Universiteit Brussel)
Nonlinear distortion analysis in circuits and systems
Prof. dr. ir. Gerd Vandersteen – Dr. ir. Ludwig De Locht (Vrije Universiteit Brussel)
This tutorial aims to demystify the nonlinear distortion analysis of circuits and systems. Combining capability of analyzing large circuits through simulation-based methods and the analytical insight provided by symbolic methods enables the analysis of the nonlinear behavior of complex systems. The simulation-based methods make it possible to pinpoint the dominant nonlinearities, while the symbolic method can be used afterwards to get an analytical insight in the nonlinear behavior. This will be demonstrated using a large set of practical examples.
The tutorial first introduces the necessary notions on Volterra theory, starting from classical linear system theory. The analytical expressions provided by Volterra result in a better understanding of the behavior of the system. The complexity of the resulting expressions, however, limits this technique to simple systems.
Second, the tutorial introduces the Best-Linear-Approximation (BLA) paradigm, which represents the nonlinear system as a linear transfer function and additive nonlinear distortion components. It enables the separation of the various linear and nonlinear contributions and is able to pinpoint the dominant nonlinear distortions in a complex system and this in a hierarchical way. The main drawback of the simulation-based methods is, however, the reduced analytical insight.
Finally, the power of both methods is combined to study a large set of application examples. Starting from a single-transistor circuit, the circuits’ complexity gradually increases to OPAMP, sigma-delta modulators and complete receiver front-end. Both the symbolically-based and the simulation-based methods are used side-by-side to gain insight in the nonlinear distortion properties of the system.
|35||On-chip Passive Components and Deep Submicron RF IC Design - John R. Long (Delft University of Technology)
On-chip Passive Components and Deep Submicron RF IC Design
John R. Long (Delft University of Technology)
Modeling, simulation, physical layout and design of monolithic passive elements for RF and high-speed applications are described in this talk. Circuit behavior and models are presented for RLC components, interconnect wiring and other distributed parameter passive elements, such as transformer baluns fabricated in modern CMOS backends. Simulation of passive components with traditional lumped-element IC (e.g., SPICE, Cadence-Spectre) simulation tools and other RF simulators (e.g., Agilent-ADS) is also covered. The advantages, limitations and trade-offs inherent in the use of on-chip passives are described using typical RF IC circuit applications.
|36||Integrated LC oscillators - Pietro Andreani (EIT)
Integrated LC oscillators
Pietro Andreani (LTH)
This tutorial lecture will go through the fundamentals of LC voltage-controlled oscillators (VCOs) integrated in CMOS processes, starting with basic linear and non-linear circuit analysis, and continuing with a rigorous yet intuitive time-variant theory of phase-noise capable of capturing the complex behavior of noise conversion into phase noise. Design for low power, low phase noise and large tuning range will be given the relevance it deserves, focusing primarily on the choice of inductor, switchable capacitors for discrete tuning, and varactors for continuous tuning.
The lecture will also include other key issues such as supply pushing, LDO-VCO co-design, routing/buffering the oscillator signals in large SoCs, and PLL-VCO co-design for fully integratable frequency synthesis. The goal it to give a thorough overview, easy to follow yet comprehensive and in touch with the latest significant research results (e.g. DCOs with extremely fine tuning steps for use in DPLLs), of one of the truly key blocks in today's and tomorrow's radios.
|37||Technology Targeting Services - Phillip Christie (imec Belgium)
Technology Targeting Services
Phillip Christie (imec Belgium)
This tutorial addresses the implications of two recent trends in the semiconductor industry. The first is a trend away from vertically integrated design and manufacturing to separate chip foundries and fabless design houses. The second is that technology offerings are becoming more application specific, since for several generations new chip designs can achieve improved speed, power, area or cost but not all at the same time. The result is growing knowledge gap between chip fabricators and designers which results in multi-million dollar decisions being made with incomplete information under very tight deadlines. The tutorial will discuss in detail a wide range of methods and tools that are under development at imec to provide businesses with the required rapid technology targeting for their products. The subjects covered will include reduced complexity device modeling, design rule generation, virtual standard cell library generation, and emulation of design flows within the Matlab programming environment using a custom Matlab toolbox. The tutorial will conclude with examples of cross-technology analysis from technology nodes ranging from 140nm to 20nm.
|38||Ultralow-power MEMS-based Radio for WBAN - Christian Enz (CSEM SA, EPFL, Switzerland)
Ultralow-power MEMS-based Radio for WBAN
Christian Enz (CSEM SA, EPFL, Switzerland)
Transceivers for wireless body area networks (WBAN) and wireless sensor networks (WSN) require both extreme miniaturization and ultra low-power dissipation in order to be seamlessly integrated virtually everywhere and enable ubiquitous connectivity among persons, objects, machines and the environment. The miniaturization challenge can be addressed with a combination of system-on-chip (SoC) and system-in-package (SiP) approaches tobuild an ultra-compact transceiver. The confined space is also limiting the available energy, which raises several design and system issues that could severely affect the radio robustness to interferers, the link budget and the autonomy. This tutorial presents how innovative narrowband radio architectures devised to take advantage and circumvent the limitations of a few well-chosen MEMS devices can address the above issues and go beyond the existing solutions both in terms of miniaturization and power dissipation reduction.
We will start with a description of the main specifications that are derived from applications for WBAN and WSN with a particular emphasis on the protocol. We then will look at the potential of using high-Q MEMS resonators in a radio transceiver and show that several fundamental building blocks can benefit from them. The main features of high-Q MEMS resonators, including the bulk acoustic wave (BAW) resonators used in the RF front-end, the RF oscillator and in the power amplifier together with silicon MEMS resonator used in the low frequency oscillators, will then be described. We will then look at different possible transceiver architectures that takeadvantage of the MEMS high-Q and circumvent their drawbacks, such as their poor frequency tunability. We will then focus on some of the main building blocks that can take advantage of high-Q resonators including the RF front-end, the RF oscillator and the power amplifier, highlighting the basic trade-offs. We will then conclude with some future perspectives on MEMS-based radio and WBAN.
|39||EDA approach to detect devices threatened by ESD cross power domain events - Louis Thiam (Cadence Design Systems, Inc.)
EDA approach to detect devices threatened by ESD cross power domain events
Louis Thiam (Cadence Design Systems, Inc.)
Modern complex SoC designed with sub-100nm CMOS process technologies could have more than a dozen global power domains for several reasons (low-power management, power separation due to noise isolation, local power up-scaling or down-scaling, ...). In 45nm CMOS process, core MOS transistor oxide thickness under the gate could be as a low as 1nm. Such devices connected to power domain signal crossings are at high risk for failing during ESD events, especially for CDM discharges.
During design phase, dedicated ESD circuitry limit voltage drop on discharge paths involved in power domain crossing even by providing an alternative low current path avoiding ESD discharge to the design core. Typically, hundreds or even thousands of such power domains crossings can occur. Just one unprotected power domain crossing can be catastrophic for the IC. Performing manual checks of each potential power domain crossing is impractical, automatic checkers are required to ensure the ESD robustness of all power domain crossings. Cadence Services has developed a software platform called EPOC (ESD Power Overcross Checker). The platform works on a hierarchical design netlist where it performs a global power domain partitioning, and use an auto-adaptive algorithm to perform a topological net-based pattern matching for identifying threatened core devices caused by ESD events on power sources. The solution has already been validated on existing 45nm designs.
The tutorial will run for 3 hours. It will be a combination of giving awareness to the students on a recent ESD issues for SoC design with respect to ESD power domain cross-checking. The tutorial will indeed go through explaining the various considerations on how ESD failure in the core SoC can occurs. Then we would see how a topological analysis base tools can be used to detects those devices that are weakly protected. I am including 2 papers reference highlighted this topic that is the resulting from the work we want to present:
• M. Khazhinsky, V. Vassilev, H. Gossner, R. Consiglio, K. Hsueh, N. Trivedi, G. Boselli, "ESD Electronic Design Automation Checks", ESD ESD Working Group, Technical Report, 2011
• M. Etherton, M. Khazhinsky, S. Lorenz, L. Thiam, L, "EDA Tool for Checking Signal Power Domain Crossings," 4 the International ESD Workshop, 2010
|40||Memory channel design issues - Hany Fahmy (Agilent)
Memory channel design issues
Hany Fahmy (Agilent)
The memory channel is found in a wide range of applications: PCs, notebooks and servers variously use DDR1/2/3 and RDRAM.
1) DDR3 can reach 17GB/s.
2) GDDR3/5 technology is widely used on graphic cards which add 3D rendering performance to PCs and game consoles. These can reach 20GB/s per GDDR5 component.
3) LPDDR2/3 are used for smartphones and tablets reaching 6.4GB/s with low power consumption down to 1.35V/1.2V for maximum battery life.
Memory architects face a tremendous challenge in the design of a memory channel for each of these applications. They have to find the optimum compromise between peak-bandwidth, power consumption and cost. To do this, successful designers use an advanced workflow and methodology supported by accurate modeling of each component of the memory channel. Unfortunately, one method can’t do it all, so an integrated toolset is required: trace and via interconnects on PCBs and packages can be modeled quickly and accurately by applying a 3D multilayer full-wave EM solver that uses the method of moments, whereas connectors are best handled using 3D arbitrary geometry full wave methods such as finite element method (FEM). Cables are best modeled by measurement-based modeling using TDR or VNA measurements. I/O buffers can be modeled either using IBIS, IBIS-AMI or netlist-based models in the time domain. SSO noise generated from the memory devices is a wide-band phenomena that best handled using time-domain 3DEM tools such as FDTD. The goal is to eliminate the noise on power/ground planes that has deleterious effects such as synchronous switching noise and EMI violations. To comply with such EMI standards as FCC or CISPR it is better to fix the emission by designing the PDN correctly, rather than being force to use spread-spectrum clocking, because the latter impairs the memory channel performance.
Agilent Advanced Design System (ADS) offers a unique, integrated workflow consisting of circuit and channel schematics and simulation as well as 3D multilayer layout and MoM EM solver. In addition, ADS includes a patented convolution engine that lets you add frequency-domain models into a time-domain simulation for eye diagram and BER contour analysis. EMPro extends ADS with 3D arbitrary geometry drawing environment and FEM and FDTD EM solvers.
|41||Ultra low voltage analog + RF design techniques - Peter Kinget (Columbia University)
Ultra low voltage analog + RF design techniques
Peter Kinget (Columbia University)
This course will review techniques to design analog and RF circuits that can operate from ultra-low upply voltages (ULV) targeted for nanoscale CMOS integration. Design examples of circuits with supplies well below 1V and as low as 0.5V will be discussed in detail illustrating ultra-low voltage design solutions at the device, circuit topology and architectural level.
|42||Thermal-Aware Design of 2D/3D Multiprocessor System-on-Chip - David Atienza (Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland)
Thermal-Aware Design of 2D/3D Multiprocessor System-on-Chip
David Atienza (Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland)
Multi-Processor Systems-on-Chips (MPSoCs) are penetrating the consumer electronics market as powerful solutions to the growing demand for scalable and high-performance systems, at limited design complexity and power dissipation.
Nevertheless, MPSoCs fabricated using the latest technology nodes are prone to alarming temperature variations on the die, which seriously decrease their expected reliability and lifetime.
Furthermore, technical advances in manufacturing technologies are fueling the trend towards high performance 3D MPSoC designs. However, 3D stacking creates higher power and heat density, leading to significantly degraded reliability and performance if thermal management is not handled properly. Thus, it is critical to develop new design methodologies that guarantee safe thermal behavior of forthcoming 2D and 3D MPSoCs at low energy and performance cost. This tutorial targets the development of dedicated system-level thermal-aware design methodologies for 2D and 3D MPSoCs that seamlessly address thermal modeling, analysis and management. In the first part of the tutorial, I will revise thermal modeling mechanisms for 2D MPSoCs based on simulation and emulation frameworks. Then, in the second part, I will introduce reactive and proactive run-time thermal management methods which prevent hot spots and large thermal gradients in 2D MPSoCs while incurring negligible performance degradation.
Finally, in the third and last part of the tutorial, I will show how new thermal modeling and active management methods, including liquid cooling, can be developed and included in 3D MPSoC architectures to achieve thermally-balanced solutions. The main concepts of the different parts of this tutorial will be illustrated by industrial case studies based on Sun’s UltraSPARC T1, Freescale and ST P2012 Multimedia SoCs and IBM 3D-stacked chip prototypes.
|43||Asynchronous logic: from principles to applications - Alex Yakovlev (Newcastle University, UK), Pascal Vivet (CEA-LETI, France)
Asynchronous logic: from principles to applications
Alex Yakovlev (Newcastle University, UK), Pascal Vivet (CEA-LETI, France)
In the course, it will be presented what are the basic principles and advantages of this type of logic, the high level modelling and synthesis related aspects, as well as system level issues such as architecture, arbitration, de-synchronization techniques.
The course will also present the Globally Asynchronous Locally Synchronous (GALS) design style, as an intermediate solution to benefit from both design paradigms, especially when used in Network-on-Chip architectures. Finally, it will be presented a state-of-the art of existing designs and start-up companies.
|Analog Design in scaled technologies (A. Baschirotto – Univ. Milan-Bicocca, S. D’Amico - Univ. Salento)|
|Leakage physics and modeling (Wieslaw Kuzmicz - Warsaw University of Technology)|
|CMOS Physics using MASTAR (Thomas Skotnicki - STMicroelectronics)
In the past, new CMOS technologies were developed based on traditional scaling of dimensions. Today in addition to dimension scaling we consider new materials (e.g. strained Silicon, different crystalline orientations, III-V high mobility channel materials, H-K dielectrics, metallic gate, etc.) and even new transistor structures (e.g. FDSOI, DG FinFET etc). This variety of options enhances strategic decision margin for the CMOS industry. On the other hand, it leads to a huge difficulty regarding quick and reliable evaluation of the options and making up optimal decisions. The traditional evaluation based on 2-D TCAD simulations is long and hardly extensible beyond the singular transistor level. An evaluation of one singular option may easily take a week of extensive TCAD simulations. Even worse is the situation if one attempts SPICE technology simulations. Here many fundamental difficulties arise.
First of all, you need specific analytical models for each material or structure. Second, you would need to implement these models and extract parameters. A huge majority of these options do not run on your line, so you do not have experimental data to run parameter extractions. A possibility then arises to replace experimental data by TCAD results. This brings us back to TCAD, but here the task is bigger, since you need not only to simulate nominal transistor but arrays of N and P transistors with variable length and width. Such a TCAD simulation task plus future parameter extraction procedures plus finally the SPICE simulations themselves may take at least one month of work. If you multiply this per the number of options and their combinations, you can easily end up with a timeframe of the action being in the order of a year. This is why we have developed MASTAR software. This is why MASTAR is now extensively used in strategic technology evaluation tasks, as well internally (industry) as at the global level (consortia, ITRS, etc).
MASTAR provides rapid evaluation of all these materials or structures (including all possible cross combinations) within a second (transistor level) or no more than minutes (circuit, system level). Thanks to that a task of building an entire Roadmap (ITRS) may be accomplished in days rather than months of work. Finally different Roadmaps can be calculated and compared within weeks instead of years. This is also why MASTAR is particularly suited for didactical purposes.
With the guidance of a Professor and with the help of the MASTAR Exercises we are providing, a student can learn and evaluate himself the advanced CMOS. He can do this within a reasonable time and without the heavy burden of TCAD simulations, inclusion of models (if available) into SPICE, parameter extractions, building test structures (layouts) and finally running SPICE simulations. Summarizing, for all students,and technology and design engineers interested in advanced CMOS, we recommend MASTAR Exercises as an easy to learn /perform passage to radically augment their level of knowledge in the field.